Assume there are more number of source files to be compiled using a set of commands everytime is a tedious process. So there is a facility to compile everything at a stretch is by the use of a Makefile.
The makefile can be named as either “Makefile” or “makefile”.
Let me define four files for my simple application, create a new directory and store all the files given below
You can download all the files here
//function.h
int sum(int,int);
void print_hello();
//hello.c
#include <stdio.h>
#include "function.h"
void print_hello()
{
printf("Hello World \n");
}
//sum.c
#include "function.h"
int sum(int a, int b)
{
int c;
c=a+b;
return c;
}
//main.c
#include <stdio.h>
#include "function.h"
int main()
{
int a=10,b=20,c;
print_hello();
c=sum(a,b);
printf("The sum of two numbers is %d ",c);
return 0;
}
There are different methods of compiling this file
Method 1: (gcc command based)
gcc main.c sum.c hello.c –o pradeep
once you execute the above command, an executable named pradeep is created and you can see the output by typing ./pradeep
Method 2: using Makefile
The basic makefile is composed of:
This syntax applied to example would look like:
target: dependencies
[tab] system command
all:
gcc main.c sum.c hello.c –o pradeep
Method 3: using Makefile with dependencies
There may be a chance of using different targets in your makefile, this is because if you modify a single file in your project, you don't have to recompile everything, only what you modified.
Here is an example
all: pradeep
hello: main.o sum.o hello.o
gcc main.o sum.o hello.o -o hello
main.o: main.c
gcc –c main.c
sum.o: sum.c
gcc –c sum.c
hello.o: hello.c
gcc –c hello.c
Method 4: using variables
CC=gcc
CFLAGS=-c -Wall
all: hello
hello: main.o sum.o hello.o
$(CC) main.o sum.o hello.o -o hello
main.o: main.c
$(CC) $(CFLAGS) main.c
sum.o: sum.c
$(CC) $(CFLAGS) sum.c
hello.o: hello.c
$(CC) $(CFLAGS) hello.c
Method 5:
With this brief introduction to Makefiles, you can create some very sophisticated mechanism for compiling your projects.
CC=gcc
CFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.c hello.c sum.c
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $@
.c.o:
$(CC) $(CFLAGS) $< -o $@
If you understand this last example, you could adapt it to your own personal projects changing only 2 lines, no matter how many additional files you have !!!.
Thanks to:http://mrbook.org/tutorials/make/
The above examples is tested only on linux and Windows also supports make utility (through nmake utility), the readers are advised to work on their own in Windows. the following link will show you the way to nmake utility
http://msdn.microsoft.com/en-us/library/dd9y37ha(VS.71).aspx
The makefile can be named as either “Makefile” or “makefile”.
Let me define four files for my simple application, create a new directory and store all the files given below
- main.c (which contains the main program)
- sum.c (summing function is defined)
- hello.c (print hello world)
- function.h (function prototypes are declared)
You can download all the files here
//function.h
int sum(int,int);
void print_hello();
//hello.c
#include <stdio.h>
#include "function.h"
void print_hello()
{
printf("Hello World \n");
}
//sum.c
#include "function.h"
int sum(int a, int b)
{
int c;
c=a+b;
return c;
}
//main.c
#include <stdio.h>
#include "function.h"
int main()
{
int a=10,b=20,c;
print_hello();
c=sum(a,b);
printf("The sum of two numbers is %d ",c);
return 0;
}
There are different methods of compiling this file
Method 1: (gcc command based)
gcc main.c sum.c hello.c –o pradeep
once you execute the above command, an executable named pradeep is created and you can see the output by typing ./pradeep
Method 2: using Makefile
The basic makefile is composed of:
This syntax applied to example would look like:
target: dependencies
[tab] system command
all:
gcc main.c sum.c hello.c –o pradeep
to run this make file(the file name should be Makefile or makefile), execute the command
make
Method 3: using Makefile with dependencies
There may be a chance of using different targets in your makefile, this is because if you modify a single file in your project, you don't have to recompile everything, only what you modified.
Here is an example
all: pradeep
hello: main.o sum.o hello.o
gcc main.o sum.o hello.o -o hello
main.o: main.c
gcc –c main.c
sum.o: sum.c
gcc –c sum.c
hello.o: hello.c
gcc –c hello.c
Method 4: using variables
CC=gcc
CFLAGS=-c -Wall
all: hello
hello: main.o sum.o hello.o
$(CC) main.o sum.o hello.o -o hello
main.o: main.c
$(CC) $(CFLAGS) main.c
sum.o: sum.c
$(CC) $(CFLAGS) sum.c
hello.o: hello.c
$(CC) $(CFLAGS) hello.c
Method 5:
With this brief introduction to Makefiles, you can create some very sophisticated mechanism for compiling your projects.
CC=gcc
CFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.c hello.c sum.c
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $@
.c.o:
$(CC) $(CFLAGS) $< -o $@
If you understand this last example, you could adapt it to your own personal projects changing only 2 lines, no matter how many additional files you have !!!.
Thanks to:http://mrbook.org/tutorials/make/
The above examples is tested only on linux and Windows also supports make utility (through nmake utility), the readers are advised to work on their own in Windows. the following link will show you the way to nmake utility
http://msdn.microsoft.com/en-us/library/dd9y37ha(VS.71).aspx
