Decimal Adder Design–VHDL

Decimal (BCD) Adder Design involves the following things

• 4bit input to 4 bit adder with A (A3 to A0) and B (B3 to B0)
• It produces output S3’ S2’ S1’ S0’ (if this number is greater than 9 (1001) then 0110 is added to it and sent to the next 4 bit adder.
• For adding 0110, a carry is generated C_N which is fed back as one of the input to the second 4 bit adder.
• Finally the output is S3 S2 S1 S0.If C_N=0 then 0000 is added to the second 4bit adder else if C_N=1 then 0110 is added to the 4 bit adder.

 

 

VHDL Program

library ieee;
use ieee.std_logic_1164.all;

entity adder is
    port(
     a,b: in bit_vector(3 downto 0);
     ci: in bit;
     s:inout bit_vector(3 downto 0);
     f:out bit_vector(3 downto 0);
     cout1:inout bit;
     cout2:out bit);
end adder;

entity fulladder is
    port(
      x,y,cin:in bit;
      sum,carry:out bit);
end fulladder;

architecture full of fulladder is
begin
    sum <= x xor y xor cin;
     carry <= ((x xor y )and cin) or (x and y);
end full;

architecture bpadder of adder is
signal c,ca:bit_vector(3 downto 1);
signal k:bit_vector(1 downto 0);

component fulladder
  port(
  x,y,cin:in bit;
  sum,carry:out bit);
end component fulladder;

begin
  FA0 :fulladder port map(a(0),b(0),ci,s(0),c(1));
  FA1 :fulladder port map(a(1),b(1),c(1),s(1),c(2));
  FA2 :fulladder port map(a(2),b(2),c(2),s(2),c(3));
  FA3 :fulladder port map(a(3),b(3),c(3),s(3),cout1);
 
  k(1) <= cout1 or (s(1)and s(3)) or (s(2) and s(3));
  k(0)<='0';
  SFA0 :fulladder port map(s(0),k(0),ci,f(0),ca(1));
  SFA1 :fulladder port map(s(1),k(1),ca(1),f(1),ca(2));
  SFA2 :fulladder port map(s(2),k(1),ca(2),f(2),ca(3));
  SFA3 :fulladder port map(s(3),k(0),ca(3),f(3),cout2);
 
end bpadder;