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Showing posts from March, 2011

Design of Embedded system

Design of embedded systems View more presentations from Pradeep Kumar S

Fault Tolerant Techniques

Fault tolerance techniques tsp View more presentations from Pradeep Kumar S

PERL - Introduction

Perl programming tsp View more presentations from Pradeep Kumar S

Real Time Database Vs General Purpose Database

Rt databases vs general purpose tsp View more presentations from Pradeep Kumar S .

MDARTS – Hard Real Time Database

Hard real time db tsp View more presentations from Pradeep Kumar S .

PERL – Regular Expression

Perl regular expr tsp View more presentations from Pradeep Kumar S .

Device Drivers for Linux - PPT

Device drivers tsp View more presentations from Pradeep Kumar S

MISRA C – Standard C for Automotive Electronics – PPT

Misra c View more presentations from Pradeep Kumar S .

OSEK – A Real Time OS for Automotive Electronics - PPT

Osek turbo View more presentations from Pradeep Kumar S .

Delay Calculation – 8051 ppt

Delay View more presentations from Pradeep Kumar S .

Inter process communication – PPT

Inter process communication View more presentations from Pradeep Kumar S .

Embedded C Programming – PPT

Embedded c programming22 for fdp View more presentations from Pradeep Kumar S .

Hardware / Software codesign - PPT

Design of embedded systems View more presentations from Pradeep Kumar S .

Network Simulator 2 - PPT

Network simulator 2 View more presentations from Pradeep Kumar S .

Mobile Applications and Project

Mobile applications and projects View more presentations from Pradeep Kumar S

Decimal Adder Design–VHDL

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Decimal (BCD) Adder Design involves the following things 4bit input to 4 bit adder with A (A3 to A0) and B (B3 to B0) It produces output S3’ S2’ S1’ S0’ (if this number is greater than 9 (1001) then 0110 is added to it and sent to the next 4 bit adder. For adding 0110, a carry is generated C N which is fed back as one of the input to the second 4 bit adder. Finally the output is S3 S2 S1 S0.If C N =0 then 0000 is added to the second 4bit adder else if C N =1 then 0110 is added to the 4 bit adder.     VHDL Program library ieee; use ieee.std_logic_1164.all; entity adder is     port(      a,b: in bit_vector(3 downto 0);      ci: in bit;      s:inout bit_vector(3 downto 0);      f:out bit_vector(3 downto 0);      cout1:inout bit;      cout2:out bit); end adder; entity fulladder is     port(       x,y,cin:in bit;       sum,carry:out bit); end fulladder; architecture full of fulladder is