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Showing posts from March, 2011

Decimal Adder Design–VHDL

Decimal (BCD) Adder Design involves the following things 4bit input to 4 bit adder with A (A3 to A0) and B (B3 to B0) It produces output S3’ S2’ S1’ S0’ (if this number is greater than 9 (1001) then 0110 is added to it and sent to the next 4 bit adder. For adding 0110, a carry is generated C N which is fed back as one of the input to the second 4 bit adder. Finally the output is S3 S2 S1 S0.If C N =0 then 0000 is added to the second 4bit adder else if C N =1 then 0110 is added to the 4 bit adder.     VHDL Program library ieee; use ieee.std_logic_1164.all; entity adder is     port(      a,b: in bit_vector(3 downto 0);      ci: in bit;      s:inout bit_vector(3 downto 0);      f:out bit_vector(3 downto 0);      cout1:inout bit;      cout2:out bit); end adder; entity fulladder is     port(       x,y,cin:in bit;       sum,carry:out bit); end fulladder; architecture full of fulladder is