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VHDL–4 to 1 Multiplexer

Multiplexer is a digital system that outputs only one from the input based on the select lines. The following diagram shows the multiplexer. In short a multiplexer is called as a MUX. Please look at the truth table also.

There are 4 inputs D0, D1, D2, and D3 and two Select lines S1 and S2. Depending upon the select line input the Dataout will have either D0 or D1 or D2 or D3.


S1 S2 Dataout
0 0 D0
0 1 D1
1 0 D2
1 1 D3

The following code shows the VHDL Program for a 4 to 1 Mux and have a look at the waveform for the MUX.

library ieee;
use ieee.std_logic_1164.all;

entity MUX is
    port (s: in std_logic_vector(1 downto 0) ;
    datain: in std_logic_vector(3 downto 0);
    dataout: out std_logic
end MUX;

architecture muxarch of mux is
        case s is
            when "00" => dataout <= datain(0);
            when "01" => dataout <= datain(1);
            when "10" => dataout <= datain(2);
            when others => dataout <= datain(3);   
        end case;
    end process;
end muxarch;



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