VHDL–3 to 8 Decoder
Decoder is a combinational logic circuit which has ‘n’ inputs and one output out of 2 n outputs. for example if there are 3 inputs the decoder asserts one of the 8 inputs to the output. the following diagram shows the 3 to 8 decoder. here is the truth table A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0