VHDL–3 to 8 Decoder

Decoder is a combinational logic circuit which has ‘n’ inputs and one output out of 2n outputs. for example if there are 3 inputs the decoder asserts one of the 8 inputs to the output. the following diagram shows the 3 to 8 decoder.

image

here is the truth table

A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0   1 0 0 0 0 0 0 0
0 0 1   0 1 0 0 0 0 0 0
0 1 0   0 0 1 0 0 0 0 0
0 1 1   0 0 0 1 0 0 0 0
1 0 0   0 0 0 0 1 0 0 0
1 0 1   0 0 0 0 0 1 0 0
1 1 0   0 0 0 0 0 0 1 0
1 1 1   0 0 0 0 0 0 0 1

Whenever the inputs are 000 then the Q0 will be ON and so on.

VHDL Code for 3 to 8 decoder

Tool used: Active HDL Student Edition 7.2

library ieee;
use ieee.std_logic_1164.all;
 
entity dec3to8 is
  port (sel: in std_logic_vector (2 downto 0);
        res: out std_logic_vector (7 downto 0));
end dec3to8;
architecture archi of dec3to8 is
  begin
    res <=  "00000001" when sel = "000" else
            "00000010" when sel = "001" else
            "00000100" when sel = "010" else
            "00001000" when sel = "011" else
            "00010000" when sel = "100" else
            "00100000" when sel = "101" else
            "01000000" when sel = "110" else
            "10000000";
end archi;

Here is the waveform

decoder

VHDL–4 to 1 Multiplexer

Multiplexer is a digital system that outputs only one from the input based on the select lines. The following diagram shows the multiplexer. In short a multiplexer is called as a MUX. Please look at the truth table also.

There are 4 inputs D0, D1, D2, and D3 and two Select lines S1 and S2. Depending upon the select line input the Dataout will have either D0 or D1 or D2 or D3.

image

S1 S2 Dataout
0 0 D0
0 1 D1
1 0 D2
1 1 D3

The following code shows the VHDL Program for a 4 to 1 Mux and have a look at the waveform for the MUX.

library ieee;
use ieee.std_logic_1164.all;

entity MUX is
    port (s: in std_logic_vector(1 downto 0) ;
    datain: in std_logic_vector(3 downto 0);
    dataout: out std_logic
    );
end MUX;

architecture muxarch of mux is
begin
    process(s,datain)
    begin
        case s is
            when "00" => dataout <= datain(0);
            when "01" => dataout <= datain(1);
            when "10" => dataout <= datain(2);
            when others => dataout <= datain(3);   
        end case;
    end process;
end muxarch;

mux

Installation of Network Simulator 2 (NS2)–Video

Installation of Network Simulator 2 in Fedora 12.

Screen Capture Software for Fedora Linux

There are two screen Capture software for Fedora which takes less space and faster to run.

1. tk-record my Desktop or qt-record my desktop

2. istanbul

to Install the above software, login as super user (root) and then give the command

yum install istanbul

yum install gtk-recordmydesktop

yum install qt-recordmydesktop

The output file what you will get will be ogv (OGG VORBIS) format which you can convert to avi or mp4 using any video converters

How to install Omnet++ in Windows 7

Installing Omnet++ in windows is a very easy task

Step 1:

Click the following link and download Omnet++ along with MinGW (Minimalist GNU for Windows – this gives the look and feel of Linux inside windows, it is similar like cygwin)

http://www.omnetpp.org/omnetpp/doc_download/2218-omnet-41-win32-source--ide--mingw-zip

Step 2:

Unzip the file to C:/

(Now your folder looks like this C:\omnetpp-4.1)

Step 3:

Open Command prompt and go to C:\omnetpp-4.1 (The command is cd \ and cd omnetpp-4.1)

Now type the command mingwenv.cmd and press enter (Please type the commands as given in the following pic)

tsp

Step 4 :

A new window will be opening which looks like a Linux Shell (as shown in the following pic)

tsp2

Step 5 :

Type the command configure (this command will check all the modules and set the path)

Type the command make (This will run for at least 10 minutes, but may vary machine to machine)

Once everything is done, you will get a successful message and type omnetpp to open the IDE

(Please Install JDK before all these steps, as Omnet++ IDE is based on Eclipse which needs JDK to be installed)