Runtime Error (Exception) Handling

ADA handles programmer defined exceptions and system defined exceptions
Some of the system defined exceptions are like 
  1. NUMERIC_ERROR - raised whenever the abnormal precision in the program like divide by zero 
  2. STORAGE-ERROR - raised whenever the program runs out of memory space
  3. CONSTRAINT_ERROR - asserts when a variable goes out of its bound
  4. TASKING_ERROR - raised during the incorrect use of tasks
  5. PROGRAM_ERROR- raised whenever an exception is not captured by any other conditions
Example on Exceptions

//Program to create two programmer defined exceptions

    if P<100>
    elseif P>150 then 
end if;
end loop;

when LOW_PRESSURE => put("Warning: Very Low Pressure");
when HIGH_PRESSURE => put ("Warning: High Pressure");

  • When exceptions are raised in multiple procedures or block and Procedures, handling the exceptions can be done using any of the procedure 
  • For Example, If there are three procedures X,Y and Z. X calls Y and Y calls Z, now there is an exception at Z (which does not have exception handler), the control will transfer the previous procedure Y (Which contains the exception handling mechanism) and handled over there.
  • Similary if a block does not have an exception handler, then the procedure which includes the block handles the expection , if that procedure contains the exception handler

Packages in ADA

Benefits of Packages
  1. Packages can be compiled, debugged independently
  2. software maintenance is very easier
  3. Once package is developed, they can be made accessible to everyone who has access to it.
  4. packages provide more security                                                                                                            
Packages contains two parts 1) a specification and 2) a body
Specification interfaces to the outside world.
body contains the executable statements associated with the functions

Examples of packages includ, COMPLEX NUMBERS Calculations, Creation of TIMER and CLOCK using packages and made as a library

//Package specification describes the functions and variables relevant to complex number and their addition and subtraction operations

type COMPLEX is 
 real, imag:float;
end record;
function ADD(a,b:COMPLEX) return COMPLEX;
function SUB(a,b:COMPLEX) return COMPLEX;

//Paackage body will implement the function specified in the package specification

package body  COMPLEX_NUMBER is
with ROOTS; //ROOTS is also a package and now used as alibrary
use ROOTS;

function ADD(a,b:COMPLEX) return COMPLEX is 
end ADD;
function SUB(a,b:COMPLEX) return COMPLEX is 
end SUB;


//Package COMPLEX_NUMBER made available as a library

with COMPLEX_NUMBER;  //retrieve the COMPLEX_NUMBER package
package CMPLXUSE is 
use COMPLEX_NUMBER; //make package available to the procedure

Blocks and Procedures in ADA

A Block in ADA contains two parts specification and a body. The specification specifies the variable used inside the block and the body executes the statement for the block


  • The main purpose of blocks are information hiding.
  • A Variable declared inside a block is accessible only within the block and nowhere outside the block.
var x,y:integer
 for x in 1..10 loop
   var x:integer;
    for x in 1..5 loop
   end loop;
end loop;

(NB: the above example shows two variables x within the block and outside the block, The x inside the block is accessible only within that block)

Procedures and Functions
  1. Blocks are repeated whenever they are needed, but functions can be written once, called anytimes
//to define a function to show the smaller among two integers
function SMALLER (A,B: integer) return integer is 
if A < B then
  return A;
return B;
end if;

//function calling SMALLER

ADA - Control Structures


if y<0>
elseif a=0 then
end if

for .... do

for i in 0..10 loop
x(i) := i * j;
end loop;


while x <>
end loop;


case x is
when 1 => y:=x;
when 2 => y:=0;
when others => y:=-1;
end case

ADA - Data types

Simple Data types
//creates three variables for TEMPERATURE which is of type float
type TEMPERATURE is new float; ta, tb, tc: TEMPERATURE;

//creates three variables for PRESSURE which is of type float
type PRESSURE is new float; pa, pb, pc: PRESSURE;
ta=pa is illegal as it is implicit type conversion
ta= TEMPERATURE(pa); is legal

//creates range between o to 10000
type HEIGHT is new float range 0..100000;

Sub types

type TIME is new float range 0..23.59; subtype MORNING is TIME range 0..11.59; subtype NOON is TIME range 12..16.00; subtype EVENING is TIME range 16.01..18.59

Enumeration type
MONTH is (jan,feb,mar,apr,may,jun,jul,aug,sep,oct,nov,dec);

floating point

type var1 is digits 8 range -1e20..1e20;
type var2 is digits 12 range -1e20..1e20;

fixed point

type var3 is delta 0.001 range 0.000..0.999;

//SMALLINT is a array variable can have the range between 0 and 20, 10 such variables are declared

type SMALLINT is integer range 0..20;
type VAR4 is array(1..10) of SMALLINT;

ADA - programming language Features

  • Object oriented programming
  • Strong typing
  • Generic programming/templates
  • Exception handling
  • Facilities for modular organization of code
  • Standard libraries for I/O, string handling, numeric computing
  • Systems programming
  • Concurrent programming
  • Real-time programming
  1. Helps for periodic and event driven tasks
  2. Avoids unbounded priority inversion
  3. Efficient implementation of Priority ceiling in ADA
  • Distributed systems programming
  • Interfaces to other languages (C, COBOL, Fortran)

Strongly Typed Language

What is a strongly typed language?
  • Each variable must be declared with its own data type
  • each data type should be associated with a value and operation (which operates on those values)
  • implicit type conversions are not allowed
  • explicit type conversions are legal.
    for example, if i is integer and a is float,
    then i=a; says it is implicit which is illegal, if i=(integer)a; then it is perfectly legal.

Myopic Offline Scheduling Algorithm

Myopic Offline Scheduling is a multiprocessor Scheduling Algorithm
  • This algorithm is meant for non preemptive tasks
  • Since it is an offline scheduling algorithm, release time, deadline and execution time are known apriori.
  • It proceeds like building up a schedule tree
  • Every level should be checked for feasibility. If not strongly feasible, then backtrack. If strongly feasible, then proceeds the next level until all the tasks are scheduled.
Heuristics are based on
  1. Deadline (Di)
  2. Earliest Start Time
  3. Laxity (Di-ei)
  4. weighted sum of any of the above
For example if the heuristics H(i) = Di, then the schedule is carried out based on the tasks with earlier deadline

Example - Multiprocessor Scheduling with precedence

The feasible interval (release Time and Deadline) of each task in the precedence graph is given next to its name. The execution time for T1,T2....T7 is respectively 2, 2, 3, 1, 1, 1, 3.
The priority is in the following order, T1>T2>T3...>T7 ( T1 being the highest priority and T7 being the Lowest Priority)
a) What is the minimum number of processors required for feasibility?

Single Processor

At time 0, T2 and T6 are ready, Since T2 is an independant task it can scheduled.
At time 1, T2 is running and T3,T5 and T6 are ready (but all are dependant tasks)
At time 2, T2 completes, T1, T3,T5 and T6 are ready (T1 is starting because of high priority)
At time 3, T1 is running,
At time 4, T1 completes, T3, T4, T5 and T6 are ready.. Here T3 is ready to execute because of high priority and as well it satisfies the precedence constraint.
At time 6, T7 is also ready along with T4, T5 and T6.

Except T5 all the tasks meets their deadlines.
So, having one processor is not a feasible schedule..

Let us try for two processors

Two Processors

In the above schedule, all the tasks meets their deadline (so this is a feasible schedule)
Ans: The minimum number of processors required by the above task set is 2.

Examples - Processor Utilisation

A system with three periodic tasks with period and its execution time T1 (3, 1) T2 (5, 2) and T3 (7, x). What is the value of x if the system uses the processor for 95% of the time?
Processor Utilisation Factor is given by
0.95 = 1/3+2/5+x/7

Example - IRIS1- Identcal Linear Reward Function

For More information about this post, Refer the Book, Real Time Systems by Krishna and Shin, McGraw Hill.

The mandatory portion of the task T4 is not meeting its deadline and it is just adjusted from the Task T2 (the mandatory portion of the task T2 is meeting its deadline, but the reward is less)

This kind of algorithm says, atleast the mandatory portion of the tasks should meet their deadlines.

IRIS Tasks (Increased Reward with Increased Service)

IRIS means Increased Reward with Increased Service,

If a task runs to its completion, it get full reward. if not run to its completion then it gets zero reward. 

So, Each IRIS tasks has two portions a Mandatory part and an Optional Part. 

If a tasks completes atleast its mandatory part, then it gets a little reward, but if a tasks does not complete even the mandatory part, then it will get zero reward from it.

so the reward function is given below, mathematically,

Where Ri(x) is the reward function, oi being the optional part and mi being the mandatory part.... 

Each task has Mi={M0.....Mn} Mandatory portions and Oi={O0...On} Optional portions
so, the execution time of the task is the sum of mandatory portion and optional portion.

The schedule is like this,
Step1; First try to schedule the task set using EDF as a whole with execution time, deadline and release time, if the task set is schedulable, the that is the feasible schedule.STOP. If not feasible, go to Step2;
Step2: Schdeule the Mandatory portion of the Task set for feasiblity using EDF. If that is also not feasible, then  that task set does not have any solution. STOP. if it is feasible go to step3:
Step3: By adjusting the mandatory task schedule and whole task schedule, we will make as scheduled...

the next post is an Example of IRIS Type1.
Source: Real Time Systems by Krishna and Shin

Shift Register


  • WARP
  • Active HDL




Program for Shift Register:
library IEEE;
use IEEE.std_logic_1164.all;
entity shiftreg is
port (
load: in STD_LOGIC;
sp: in STD_LOGIC;
clk: in STD_LOGIC;
si: in STD_LOGIC;
pi: in STD_LOGIC_VECTOR (3 downto 0);
s0: out STD_LOGIC;
p0: out STD_LOGIC_VECTOR (3 downto 0)
end shiftreg;
architecture shiftreg of shiftreg is
signal storage:std_logic_vector(3 downto 0) :="XXXX";
variable i:integer := 1;
if(load = '1')then
case sp is
when '1' =>
storage <= pi;
when '0' =>
if i<5 then
storage(i-1) <= si;
i :=i+1;
end if;
when others => null;
end case;
case sp is
when '1' =>
when '0' =>
if i<5 then
s0 <= storage(i-1);
end if;
when others => null;
end case;
end if;
end process;
end shiftreg;