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Simulation of D Flip Flop and J-K Flip Flop

Requirements:

  • WARP
  • Active HDL
  • Cool Runner and Fitter CPLD Kit

D Flip Flop

image

 

Program for D Flip flop
Library ieee;
Use ieee.std_logic_1164.all;
entity dff is
port (
clk: in BIT;
data: in BIT;
q: out BIT;
qbar: out BIT
);
end dff;
architecture dff of dff is
begin
process(clk,data)
begin
if(clk='1') then
q <= data;
qbar <= not data;
end if;
end process;
end dff;

Waveform (D Flip Flop)

image

JK Flip Flop

image

 

Program for J-K flip flop
library IEEE;
use IEEE.std_logic_1164.all;
entity jkff is
port (
clk: in STD_LOGIC;
j: in STD_LOGIC;
k: in STD_LOGIC;
q: inout STD_LOGIC;
qbar: inout STD_LOGIC
);
end jkff;
architecture jkff of jkff is
begin
process(clk)
begin
if(clk'event and clk='1') then
if(j = not k) then
q <= j;
qbar <= k;
elsif(j = '1' and k = '1') then
q <= not q;
qbar <= not qbar;
end if;
end if;
end process;
end jkff;

Waveform (JK Flip Flop)

image

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