4 bit Magnitude Comparator

Requirements:

  • WARP
  • Active HDL
  • Cool Runner and Fitter CPLD Kit

 

Program for Magnitude Comparator
library IEEE;
use IEEE.std_logic_1164.all;
entity mag_comp is
port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
eq: out STD_LOGIC;
agr: out STD_LOGIC;
bgr: out STD_LOGIC
);
end mag_comp;
architecture mag_comp of mag_comp is
begin
process(a,b)
begin
eq <= '0';
agr <= '0';
bgr <= '0';
if (a=b) then
eq <= '1';
elsif(a>b) then
agr <= '1';
elsif(b>a) then
bgr <= '1';
end if;
end process;
end mag_comp;

Symbol

image

Waveform

image

Example – Rate Monotonic Scheduling

pics 011    pics 012pics 013

pics 015

 

Bin Packing Assignment algorithm for EDF Scheduling

  1. This algorithm is for independent preemptible tasks.
  2. All the processors are identical. The tasks requires no resources except the processor time
  3. The period is equal to the relative deadline.
  4.  

    The sum of utilisations of the tasks assigned to a processor is always less than or equal to 1, the task set is EDF scheduled in that processor.

    So, the problme reduces to making task assignments with the property that the sum of the utilisations of the tasks assigned to a processor does not exceed to 1.

     

     

    T1

    T2

    T3

    T4

    T5

    T6

    T7

    T8

    T9

    T10

    T11

    ei

    5

    7

    3

    1

    10

    16

    1

    3

    9

    17

    21

    Pi

    10

    21

    22

    24

    30

    40

    50

    55

    70

    90

    95

    u(i)

    =ei/Pi

    0.50

    0.33

    0.14

    0.04

    0.33

    0.40

    0.02

    0.05

    0.13

    0.19

    0.22

     

    Arrange the tasks in the order of their utilisation

     

    So the order will be L={T1,T6,T2,T5,T11,T10,T3,T9,T8,T4,T7}

     

    style="border-style:solid;border-color:#A3A3A3;border-width:1pt; vertical-align:top;width:1.4701in;padding:4pt 4pt 4pt 4pt">

    0.33

    Tasks

    u(i) -> utilisation

    Processor pi

    Assignment Vector(U)

    T1

    0.50

    p1

    (0.50)

    T6

    0.40

    p1

    (0.90)

    T2

    0.33

    p2

    (0.90, 0.33)

    T5

    p2

    (0.90,0.66)

    T11

    0.22

    p2

    (0.90,0.88)

    T10

    0.19

    p3

    (0.90,0.88,0.19)

    T3

    0.14

    p3

    (0.90,0.88,0.33)

    T9

    0.13

    p3

    (0.90,0.88,0.46)

    T8

    0.05

    p1

    (0.95,0.88,0.46)

    T4

    0.04

    p1

    (0.99,0.88,0.46)

    T7

    0.02

    p2

    (0.99,0.90,0.46)

     

     

    Steps

  5. When T1 is scheduled, there is only one processor with utilisation 0.5, so T1 is allocated to p1
  6. When T6 comes, again p1 can accommodate as 0.5+0.4=0.9 which is again less than total utilisation factor 1.
  7. When T2 comes, its utilisation is 0.33 which cant be added to p1 since it will cross 1, so a new processor is added and it is p2.
  8. Like wise all other tasks are scheduled according to their utilisation factor.
  9.  


    >The Final schedule is given below

    p1=> T1, T6,T8,T4

    p2=> T2,T5,T11,T7

    p3 => T10,T3,T9

     

Next fit Algorithm for RM Scheduling

  1. This algorithm uses the same assumptions used in the Rate Monotonic Scheduling
  2. This algorithm is based on the RM Scheduling algorithm for each processors
  3. The multi processor is assumed to consists of identical processors.
  4. The tasks are assumed to require no resources other than the CPU Time
  5.  

    The tasks are allocated to processors according to the classes in which they belong. Each classes contains a set of processors that is only allocated the tasks of that class.

     

    Tasks are allocated one by one to the appropriate processor classes until all the tasks have been scheduled.

    If any class fails to produce a feasible RM Schedule, then a new processor will be added to the same class and the corresponding task (which does not meets its deadline) is allocated to the new processor class.

     

    Example

    Let us say M=4 classes. The following table lists the classes

    Class

    Bound

    C1

    (0.41,1]

    C2

    (0.26,0.41]

    C3

    (0.19,0.26]

    C4

    (0, 0.19]

     

    The tasks sets are given below

     

    T1

    T2

    T3

    T4

    T5

    T6

    T7

    T8

    T9

    T10

    T11

    ei

    5

    7

    3

    1

    10

    16

    1

    3

    9

    17

    21

    Pi

    10

    21

    22

    24

    30

    40

    50

    55

    70

    90

    95

    u(i)=ei/Pi

    0.50

    0.33

    0.14

    0.04

    0.33

    0.40

    0.02

    0.05

    0.13

    0.19

    0.22

    Class

    C1

    C2

    C4

    C4

    C2

    C2

    C4

    C4

    C4

    C4

    C3

     

    Steps

  6. Since C1 class contains only one task T1, it will be RM Schedulable, so p1 is a processor under C1
  7. C2 contains three tasks, T2, T5 and T6, upon RM Scheduling T6 fails to meets its deadline, so a new processor is added to class C2. So class C2 contains two processors p2 and p5
  8. C3 is also having only one Task T11 and it will also be schedulable under RM, so p3 is a processor under C3.
  9. C4 contains 6 tasks namely, T3,T4, T7,T8,T9 and T10. All the tasks meets their deadlines under RM Scheduling, so p4 is a processor under C4
  10.  

    Processor

    Tasks

    p1

    T1

    p2

    T2, T5

    p3

    T11

    p4

    T3,T4,T7,T8,T9,T10

    p5

    T6

     

     

Priority Inheritance Protocol

    The use of Priority inheritance allows to avoid the priority inversion problem.

     

    Under this scheme, if a high priority task T1 is blocked by a lower priority task T2 (because T2 is currently executing a critical section needed by T1), the lower priority task temporarily inherits the priority of T1. When the blocking stops, T2 resumes its original priority.

     

  1. If a task T1 is blocked by T2 (due to contention for a critical section) and The priority of T1 is greater than T2, task T2 inherits the priority of T1 as long as it blocks T1. when T2 exits the critical section, it reverts to its original priority .
  2.  

  3. Priority inheritance is transitive. If T3 blocks, which blocks T1(with T1 being the highest priority, T2 the medium priority and T3 being the lower priority), then T3 inherits the priority of T1 through T2.
  4.  

    Disadvantages of PIP

    Priority inheritance can lead to deadlock during the following situation

     

    Consider two tasks T1 and T2 uses two critical sections S1 and S2 in the following order

     

    T1: Lock S1; Lock S2;Unlock S2; Unlock S1

    T2: Lock S2; Lock S1;Unlock S1; Unlock S2

     

  5. Assume T1 is having higher priority over T2.  Suppose T2 starts execution at Time t0. At time t1, it locks S2.
  6. At time t2, T1 is initiated and it preempts T2 owing to its higher priority.
  7. At time t3, T1 locks S1.
  8. At time t4, T1 attempts to lock S2, which is being locked by T2. so T2 inherits the priority of T1 and starts executing,
  9. At time t5, T2 tries to lock S1, which is locked by T1.
  10. So both the tasks are now deadlocked.
  11.  

    This problem can be avoided by means of implementing priority Ceiling protocol

Simulation of Synchronous and Asynchronous counters

Requirements:

  • WARP
  • Active HDL
  • Cool Runner and Fitter CPLD Kit

Program for Asynchronous counter:
Library ieee;
Use ieee.std_logic_1164.all;
entity asyn_counter is
port (
clk: in BIT;
ce: in BIT;
clear: in BIT;
load: in BIT;
dir: in BIT;
p: in INTEGER range 0 to 255;
qd: out INTEGER range 0 to 255
);
end asyn_counter;
architecture asyn_counter of asyn_counter is
begin
process(clk,clear,load)
variable count : integer range 0 to 255;
begin
if(clear = '0') then
count := 0;
elsif(load = '1' and clear = '1') then
if(ce = '1' and dir = '0') then
count := count + 0;
elsif(ce = '1' and dir = '1') then
count := count + 1;
end if;
end if;
qd <= count;
end process;
end asyn_counter;

Asynchronous counter

image 

 

image

 

Synchronous Counter

Program for Synchronous Counter
library IEEE;
use IEEE.std_logic_1164.all;
entity syn_counter is
port (
clk: in STD_LOGIC;
ce: in STD_LOGIC;
clear: in STD_LOGIC;
load: in STD_LOGIC;
direction: in STD_LOGIC;
pre_value: in INTEGER range 0 to 15;
output: out INTEGER range 0 to 15
);
end syn_counter;
architecture syn_counter of syn_counter is
begin
process(clk)
variable temp: integer range 0 to 15;
begin
if(rising_edge(clk)) then
if(clear = '0') then
temp := 0;
elsif(load = '1') then
temp := pre_value;
elsif(ce='1' and direction = '0') then
temp := (temp -1) mod 16;
elsif(ce = '1' and direction = '1') then
temp := (temp +1) mod 16;
end if;
end if;
output <= temp;
end process;
end syn_counter;

image

 

image

Simulation of Look Ahead Carry Generator

Requirements:

  • WARP
  • Active HDL

Design:

 

image

Program for the Look Ahead Carry Generator
library IEEE;
use IEEE.std_logic_1164.all;
entity look_ahead_carry is
port (
a: in STD_LOGIC_VECTOR (4 downto 1);
b: in STD_LOGIC_VECTOR (4 downto 1);
c0: in STD_LOGIC;
c: out STD_LOGIC_VECTOR (4 downto 1)
);
end look_ahead_carry;
architecture arch_look_ahead_carry of look_ahead_carry is
signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic;
begin
s1 <= a(1) and b(1);
s2 <= a(1) or b(1);
s3 <= a(2) and b(2);
s4 <= a(2) or b(2);
s5 <= a(3) and b(3);
s6 <= a(3) or b(3);
s7 <= a(4) and b(4);
s8 <= a(4) or b(4);
c(1) <= s1 or (c0 and s2);
c(2) <= s3 or (s1 and s4) or (c0 and s2 and s4);
c(3) <= s5 or (s3 and s6) or (s1 and s4 and s6) or (c0 and s2 and s4 and s6);
c(4) <= s7 or (s5 and s8) or (s3 and s6 and s8) or (s1 and s4 and s6 and s8)
or (c0 and s2 and s4 and s6 and s8);
end arch_look_ahead_carry;

Waveform

image

Simulation of BCD to Gray Code Conversion

Requirements:

  • WARP
  • Active HDL

Procedure:

  • The Specification of the BCD to GRAY Code Converter is taken.
  • The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary.
  • Entity and Architecture is created for the above specification.
  • The Result is verified by simulation and the waveforms are seen.

Design:
image

Program for BCD to Gray Conversion:
library IEEE;
use IEEE.std_logic_1164.all;
entity bcdtogray is
port (
w: in STD_LOGIC;
x: in STD_LOGIC;
y: in STD_LOGIC;
z: in STD_LOGIC;
a: out STD_LOGIC;
b: out STD_LOGIC;
c: out STD_LOGIC;
d: out STD_LOGIC
);
end bcdtogray;
architecture archbcdtogray of bcdtogray is
begin
a <= w and (not x) and (not y);
b <= (w and (not x) and (not y)) or (not w and x);
c <= (not w) and (x xor y);
d <= (not w) and (y xor z);
end archbcdtogray;

Waveform

image

How to Correct the NS / NAM Problem in Fedora 10

Step 1: download the NS allinone Package from the following link. I Used (ns-allinone2.33).
Step 2: extract it in a folder (Eg: I used /opt/), but you need to be a root to extract in that folder (better extract it under /home/#username#)

NAM wont work because of the compatibility issues with tk8.4.18, so download a patch given in the following link.

Step 3: http://bugs.gentoo.org/show_bug.cgi?id=225999
Step 4: There are two patch files, the second file worked in my case as i tried only the second file (tk-8.4-lastevent.patch)
Step 5: Save the file as .patch and store it in ./ns-allinone-2.33/tk8.4.18/

Step 6: Patch the file by executing the following commands

[rootamiitesh tk8.4.18]$ patch -p1 < /opt/ns-allinone-2.33/tk8.4.18/tk-8.4-lastevent.patch

(you may get the following lines of information...)

can't find file to patch at input line 3
Perhaps you used the wrong -p or --strip option?
The text leading up to this was:
--------------------------
|--- generic/tk.h.orig 2008-02-06 16:31:40.000000000 +0100
|+++ generic/tk.h 2008-07-24 08:21:46.000000000 +0200
--------------------------
File to patch: generic/tk.h

Step 7: Enter the file to patch as generic/tk.h

Thats it!!!!!

Step 8: then go for the Installing the Network Simulator 2
click here to see the installation instructions

Priority Inversion Problem

Priority Inversion Problem
  • In Scheduling, priority inversion is the scenario where a low priority Task holds a shared resource, that is required by a high priority task.
  • This causes the execution of the high priority task to be blocked until the low priority task has released the resource, effectively "inverting" the relative priorities of the two tasks.
  • If some other medium priority task, one that does not depend on the shared resource, attempts to run in the interim, it will take precedence over both the low priority task and the high priority task.
Priority Inversion will
  • make problems in real time systems.
  • reduce the performance of the system
  • may reduce the system responsiveness which leads to the violation of response time guarantees.
This problem can be avoided by implementing
  1. Priority Inheritance Protocol (PIP) or
  2. Priority Ceiling Protocol (PCP)

Resources and Critical Section

A task that is currently holding a unsharable resource is said to be in critical section associated with that resource.
  • Locking the resource mainly achieved by means of Binary Semaphores.
  • When a task wants to enter a critical section, it first checks whether the corresponding semaphore is taken or not. If the semaphore is locked,then the task will wait until the semaphore is unlocked.
  • Critical Sections are always properly nested Lock R1; Lock R2; Unlock R2; unlock R1.Where R1 and R2 are two resources.
Sharing a resource always leads to Priority Inversion Problem, that a high priority task is waiting to run under a CPU, whereas the low priority tasks are running locking a resource.

Baud Rate Generator

Requirements:

  • WARP
  • Active HDL

Procedure:

  • The Specifications of the Baud Rate are chosen.
  • The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary.
  • Entity and Architecture is created for the above specification.
  • The Result is verified by simulation and the waveforms are seen.

Program for Baud Rate Generator
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity baud_gen_latest is
Port (
Sysclk: in STD_LOGIC;
rst_b: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (2 downto 0);
baclkx8: buffer STD_LOGIC;
bcclk: out STD_LOGIC
);
end baud_gen_latest;
architecture baud_gen_latest of baud_gen_latest is
Signal ctr1:std_logic_vector (3 downto 0):= "0000";
Signal ctr2:std_logic_vector (7 downto 0):= "00000000";
Signal ctr3:std_logic_vector (2 downto 0):= "000";
signal clkdiv:std_logic_vector(3 downto 0) := "0000";
begin
process(sysclk)
begin
if(sysclk'event and sysclk = '1') then
if(ctr1="1100") then ctr1 <= "0000";
else ctr1 <= ctr1 +1;
end if;
end if;
end process;
clkdiv <= ctr1 + 1;
process(clkdiv(3))
begin
if(rising_edge(clkdiv(3))) then
ctr2 <= ctr2 +1;
end if;
end process;
process(clkdiv(3))
begin
if (sel = "000") then
baclkx8 <= ctr2(0);
elsif sel = "001" then
baclkx8 <= ctr2(1);
end if;
end process;
process(baclkx8)
begin
if(rising_edge(baclkx8)) then
ctr3 <= ctr3 +1;
end if;
end process;
bcclk <= ctr3(2);
end baud_gen_latest;

image

Waveform:

image

Simulation of Arithmetic and Logic Unit (ALU)

Requirements:

  • WARP
  • Active HDL

Procedure:

  • The Specifications of the Baud Rate are chosen.
  • The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary.
  • Entity and Architecture is created for the above specification.
  • The Result is verified by simulation and the waveforms are seen.

Program for Baud Rate Generator
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity baud_gen_latest is
Port (
Sysclk: in STD_LOGIC;
rst_b: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (2 downto 0);
baclkx8: buffer STD_LOGIC;
bcclk: out STD_LOGIC
);
end baud_gen_latest;
architecture baud_gen_latest of baud_gen_latest is
Signal ctr1:std_logic_vector (3 downto 0):= "0000";
Signal ctr2:std_logic_vector (7 downto 0):= "00000000";
Signal ctr3:std_logic_vector (2 downto 0):= "000";
signal clkdiv:std_logic_vector(3 downto 0) := "0000";
begin
process(sysclk)
begin
if(sysclk'event and sysclk = '1') then
if(ctr1="1100") then ctr1 <= "0000";
else ctr1 <= ctr1 +1;
end if;
end if;
end process;
clkdiv <= ctr1 + 1;
process(clkdiv(3))
begin
if(rising_edge(clkdiv(3))) then
ctr2 <= ctr2 +1;
end if;
end process;
process(clkdiv(3))
begin
if (sel = "000") then
baclkx8 <= ctr2(0);
elsif sel = "001" then
baclkx8 <= ctr2(1);
end if;
end process;
process(baclkx8)
begin
if(rising_edge(baclkx8)) then
ctr3 <= ctr3 +1;
end if;
end process;
bcclk <= ctr3(2);
end baud_gen_latest;

image

 

image

Earliest Deadline First (EDF) - Example

There are Four Tasks T1,T2,T3 and T4 with its release time, execution time and absolute Deadlines
T1(0,4,15)
T2(0,3,12)
T3(2,5,9)
T4(5,2,8)

At time 0, Task T1 and T2 are ready; T2 is having earlier deadline, so T2 is having higher priority
At time 2, T3 releases; and it preempts T2
at time 5, T4 releases; and it preempts T3 and completes it execution
at time 7, T3 resumes and completes;
at time 9, T2 resumes and completes;
at time 10, T1 starts and completes;

The following Diagram represents this


MISRA C

What is Misra C

Motor Industries Software Reliability Association

This Standard originally developed for the Automotive Industry

It produces safe and robust C.

MISRA C includes 127 rules. 93 of these are required and the remaining 34 are advisory. All rules apply to the source code and not to the object code generated by the compiler.

MISRA C 2004

121 RULES REQUIRED

20 RULES ADVISORY

21 Categories

 

MISRA C 2004 Categories

In the group ‘Conversions’, the use of implicit type conversions as well as redundant explicit casts are prohibited.

In the group ‘Expressions’, a rule describes floating-point variables are not to be tested for exact equality or inequality.

In the group ‘Control Flow’, the use of goto, break and continue is prohibited. Also a number of constraints on the use of the if, else, switch, and case constructs is defined.

The group ‘Pointers and Arrays’ prohibits the use of non-constant pointers to functions and discourages the use of pointer arithmetic at all.

The group ‘Structures and Unions’ requires that all structure/ union members are named and referred to by name only.

Rules of Misra c

Rule 3

Assembly code and C should not be mixed.

Real time behavior, size and other issues may require the use of assembly code.

In this case, the mixing of the codes should be via a well defined interface.

RULE 6

Character and string literal shall only contain that map to the subset of ISO 10646. Because characters are not portable between implementations.

Rule 9

Nested Comments should flag as an error

Example

/*Comment

Perform_critical_thing(X);

/* Safe functionality */

Rule 13 and 17

In the group ‘Types’, the basic types char, int, short, long, float and double should be replaced with typedefs indicating the specific length (e.g., SI_16 for a 16 bit signed integer) and the type char shall always be declared as either unsigned char or signed char.

Typedefs should not be reused as other typedefs for any other purpose within the same project.

Eg:

typedef int int_16a;

#define int int_16a

(both should not be declared)

Rule 19 violation:

Octal Constants (other than zero) shall not be used

A = 111;

B = 101;

C = 011;

Rule 20 (required):

All object and function identifiers shall be declared before use.

Rule 35 and 36

Assignment operators shall not be used in Boolean expressions

if ((x = y) != 0)

bitwise operators shall not be used inboolean expressions

Rule 40

If the sizeof operator is used on an expression, it should not contain any side effects

Eg:

int x,y;

y=sizeof(x=1234);

// y should be assigned the value of sizeof(i) which is an integer and it is not like 1234 is assigned to i

rule 43 violation:

MY_UCHAR uc;

MY_SHORT si;

...

uc=si;

Don’t use implicit conversions which may result in information loss

MISRA C rule 50 violation:

if (EF==0)

Floating Point variables shall not be tested for exact equality or inequality

Rule 63

The switch statement should not be used for only two cases, in that case if else should be used

rule 65 violation:

for (F=0.0; F<10.0; F++)

Floating Point variables shall not be used as loop counters

Rule 83

Functions with non void return type shall not be terminated with implicit return type. It shall have an explicit return statement

Rule 118

Use of calloc, malloc and realloc is strictly banned.

Simulation of D Flip Flop and J-K Flip Flop

Requirements:

  • WARP
  • Active HDL
  • Cool Runner and Fitter CPLD Kit

D Flip Flop

image

 

Program for D Flip flop
Library ieee;
Use ieee.std_logic_1164.all;
entity dff is
port (
clk: in BIT;
data: in BIT;
q: out BIT;
qbar: out BIT
);
end dff;
architecture dff of dff is
begin
process(clk,data)
begin
if(clk='1') then
q <= data;
qbar <= not data;
end if;
end process;
end dff;

Waveform (D Flip Flop)

image

JK Flip Flop

image

 

Program for J-K flip flop
library IEEE;
use IEEE.std_logic_1164.all;
entity jkff is
port (
clk: in STD_LOGIC;
j: in STD_LOGIC;
k: in STD_LOGIC;
q: inout STD_LOGIC;
qbar: inout STD_LOGIC
);
end jkff;
architecture jkff of jkff is
begin
process(clk)
begin
if(clk'event and clk='1') then
if(j = not k) then
q <= j;
qbar <= k;
elsif(j = '1' and k = '1') then
q <= not q;
qbar <= not qbar;
end if;
end if;
end process;
end jkff;

Waveform (JK Flip Flop)

image