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Showing posts from January, 2009

4 bit Magnitude Comparator

Requirements:WARP Active HDL Cool Runner and Fitter CPLD Kit Program for Magnitude Comparator
library IEEE;
use IEEE.std_logic_1164.all;
entity mag_comp is
port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
eq: out STD_LOGIC;
agr: out STD_LOGIC;
bgr: out STD_LOGIC
);
end mag_comp;
architecture mag_comp of mag_comp is
begin
process(a,b)
begin
eq <= '0';
agr <= '0';
bgr <= '0';
if (a=b) then
eq <= '1';
elsif(a>b) then
agr <= '1';
elsif(b>a) then
bgr <= '1';
end if;
end process;
end mag_comp;SymbolWaveform

Bin Packing Assignment algorithm for EDF Scheduling

This algorithm is for independent preemptible tasks.All the processors are identical. The tasks requires no resources except the processor timeThe period is equal to the relative deadline.The sum of utilisations of the tasks assigned to a processor is always less than or equal to 1, the task set is EDF scheduled in that processor.So, the problme reduces to making task assignments with the property that the sum of the utilisations of the tasks assigned to a processor does not exceed to 1.T1T2T3T4T5T6T7T8T9T10T11ei573110161391721Pi1021222430405055709095u(i)=ei/Pi0.500.330.14

Next fit Algorithm for RM Scheduling

This algorithm uses the same assumptions used in the Rate Monotonic SchedulingThis algorithm is based on the RM Scheduling algorithm for each processorsThe multi processor is assumed to consists of identical processors.The tasks are assumed to require no resources other than the CPU TimeThe tasks are allocated to processors according to the classes in which they belong. Each classes contains a set of processors that is only allocated the tasks of that class.Tasks are allocated one by one to the appropriate processor classes until all the tasks have been scheduled.If any class fails to produce a feasible RM Schedule, then a new processor will be added to the same class and the corresponding task (which does not meets its deadline) is allocated to the new processor class.ExampleLet us say M=4 classes. The following table lists the classes ClassBoundC1(0.41,1]C2(0.26,0.41]C3(0.19,0.26]C4(0, 0.19] The tasks sets are given belowT1T2T3T4T5T6T7T8T9T10T11ei5731101…

Priority Inheritance Protocol

The use of Priority inheritance allows to avoid the priority inversion problem. Under this scheme, if a high priority task T1 is blocked by a lower priority task T2 (because T2 is currently executing a critical section needed by T1), the lower priority task temporarily inherits the priority of T1. When the blocking stops, T2 resumes its original priority. If a task T1 is blocked by T2 (due to contention for a critical section) and The priority of T1 is greater than T2, task T2 inherits the priority of T1 as long as it blocks T1. when T2 exits the critical section, it reverts to its original priority .Priority inheritance is transitive. If T3 blocks, which blocks T1(with T1 being the highest priority, T2 the medium priority and T3 being the lower priority), then T3 inherits the priority of T1 through T2. Disadvantages of PIPPriority inheritance can lead to deadlock during the following situationConsider two tasks T1 and T2 uses two critical s…

Simulation of Synchronous and Asynchronous counters

Requirements:WARP Active HDL Cool Runner and Fitter CPLD Kit Program for Asynchronous counter:
Library ieee;
Use ieee.std_logic_1164.all;
entity asyn_counter is
port (
clk: in BIT;
ce: in BIT;
clear: in BIT;
load: in BIT;
dir: in BIT;
p: in INTEGER range 0 to 255;
qd: out INTEGER range 0 to 255
);
end asyn_counter;
architecture asyn_counter of asyn_counter is
begin
process(clk,clear,load)
variable count : integer range 0 to 255;
begin
if(clear = '0') then
count := 0;
elsif(load = '1' and clear = '1') then
if(ce = '1' and dir = '0') then
count := count + 0;
elsif(ce = '1' and dir = '1') then
count := count + 1;
end if;
end if;
qd <= count;
end process;
end asyn_counter;Asynchronous counterSynchronous CounterProgram for Synchronous Counter
library IEEE;

Simulation of Look Ahead Carry Generator

Requirements:WARP Active HDL Design:Program for the Look Ahead Carry Generator
library IEEE;
use IEEE.std_logic_1164.all;
entity look_ahead_carry is
port (
a: in STD_LOGIC_VECTOR (4 downto 1);
b: in STD_LOGIC_VECTOR (4 downto 1);
c0: in STD_LOGIC;
c: out STD_LOGIC_VECTOR (4 downto 1)
);
end look_ahead_carry;
architecture arch_look_ahead_carry of look_ahead_carry is
signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic;
begin
s1 <= a(1) and b(1);
s2 <= a(1) or b(1);
s3 <= a(2) and b(2);
s4 <= a(2) or b(2);
s5 <= a(3) and b(3);
s6 <= a(3) or b(3);
s7 <= a(4) and b(4);
s8 <= a(4) or b(4);
c(1) <= s1 or (c0 and s2);
c(2) <= s3 or (s1 and s4) or (c0 and s2 and s4);
c(3) <= s5 or (s3 and s6) or (s1 and s4 and s6) or (c0 and s2 and s4 and s6);
c(4) <= s7 or (s5 and s8) or (s3 and s6 and s8) or (s1 and s4 and s6 and s8)
or …

Simulation of BCD to Gray Code Conversion

Requirements:WARP Active HDL Procedure:The Specification of the BCD to GRAY Code Converter is taken. The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary. Entity and Architecture is created for the above specification. The Result is verified by simulation and the waveforms are seen. Design:
Program for BCD to Gray Conversion:
library IEEE;
use IEEE.std_logic_1164.all;
entity bcdtogray is
port (
w: in STD_LOGIC;
x: in STD_LOGIC;
y: in STD_LOGIC;
z: in STD_LOGIC;
a: out STD_LOGIC;
b: out STD_LOGIC;
c: out STD_LOGIC;
d: out STD_LOGIC
);
end bcdtogray;
architecture archbcdtogray of bcdtogray is
begin
a <= w and (not x) and (not y);
b <= (w and (not x) and (not y)) or (not w and x);
c <= (not w) and (x xor y);
d <= (not w) and (y xor z);
end archb…

How to Correct the NS / NAM Problem in Fedora 10

Step 1: download the NS allinone Package from the following link. I Used (ns-allinone2.33).
Step 2: extract it in a folder (Eg: I used /opt/), but you need to be a root to extract in that folder (better extract it under /home/#username#)

NAM wont work because of the compatibility issues with tk8.4.18, so download a patch given in the following link.

Step 3: http://bugs.gentoo.org/show_bug.cgi?id=225999
Step 4: There are two patch files, the second file worked in my case as i tried only the second file (tk-8.4-lastevent.patch)
Step 5: Save the file as .patch and store it in ./ns-allinone-2.33/tk8.4.18/

Step 6: Patch the file by executing the following commands

[rootamiitesh tk8.4.18]$ patch -p1 < /opt/ns-allinone-2.33/tk8.4.18/tk-8.4-lastevent.patch

(you may get the following lines of information...)

can't find file to patch at input line 3
Perhaps you used the wrong -p or --strip option?
The text leading up to this was:
--------------------------
|--- generic/tk.h.orig 2008-02-06 16:31:4…

Priority Inversion Problem

Priority Inversion Problem
In Scheduling, priority inversion is the scenario where a low priority Task holds a shared resource, that is required by a high priority task.This causes the execution of the high priority task to be blocked until the low priority task has released the resource, effectively "inverting" the relative priorities of the two tasks. If some other medium priority task, one that does not depend on the shared resource, attempts to run in the interim, it will take precedence over both the low priority task and the high priority task.Priority Inversion will make problems in real time systems.reduce the performance of the systemmay reduce the system responsiveness which leads to the violation of response time guarantees.
This problem can be avoided by implementing
Priority Inheritance Protocol (PIP) orPriority Ceiling Protocol (PCP)

Resources and Critical Section

A task that is currently holding a unsharable resource is said to be in critical section associated with that resource.
Locking the resource mainly achieved by means of Binary Semaphores.When a task wants to enter a critical section, it first checks whether the corresponding semaphore is taken or not. If the semaphore is locked,then the task will wait until the semaphore is unlocked.Critical Sections are always properly nested Lock R1; Lock R2; Unlock R2; unlock R1.Where R1 and R2 are two resources.
Sharing a resource always leads to Priority Inversion Problem, that a high priority task is waiting to run under a CPU, whereas the low priority tasks are running locking a resource.

Baud Rate Generator

Requirements:WARP Active HDL Procedure:The Specifications of the Baud Rate are chosen. The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary. Entity and Architecture is created for the above specification. The Result is verified by simulation and the waveforms are seen. Program for Baud Rate Generator
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity baud_gen_latest is
Port (
Sysclk: in STD_LOGIC;
rst_b: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (2 downto 0);
baclkx8: buffer STD_LOGIC;
bcclk: out STD_LOGIC
);
end baud_gen_latest;
architecture baud_gen_latest of baud_gen_latest is
Signal ctr1:std_logic_vector (3 downto 0):= "0000";
Signal ctr2:std_logic_vector (7 downto 0):= "00000000";
Signal ctr3:std_log…

Simulation of Arithmetic and Logic Unit (ALU)

Requirements:WARP Active HDL Procedure:The Specifications of the Baud Rate are chosen. The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary. Entity and Architecture is created for the above specification. The Result is verified by simulation and the waveforms are seen. Program for Baud Rate Generator
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity baud_gen_latest is
Port (
Sysclk: in STD_LOGIC;
rst_b: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR (2 downto 0);
baclkx8: buffer STD_LOGIC;
bcclk: out STD_LOGIC
);
end baud_gen_latest;
architecture baud_gen_latest of baud_gen_latest is
Signal ctr1:std_logic_vector (3 downto 0):= "0000";
Signal ctr2:std_logic_vector (7 downto 0):= "00000000";
Signal ctr3:std_logic_vecto…

Earliest Deadline First (EDF) - Example

There are Four Tasks T1,T2,T3 and T4 with its release time, execution time and absolute DeadlinesT1(0,4,15) T2(0,3,12) T3(2,5,9) T4(5,2,8)
At time 0, Task T1 and T2 are ready; T2 is having earlier deadline, so T2 is having higher priority At time 2, T3 releases; and it preempts T2 at time 5, T4 releases; and it preempts T3 and completes it execution at time 7, T3 resumes and completes; at time 9, T2 resumes and completes; at time 10, T1 starts and completes;
The following Diagram represents this

MISRA C

What is Misra CMotor Industries Software Reliability AssociationThis Standard originally developed for the Automotive IndustryIt produces safe and robust C. MISRA C includes 127 rules. 93 of these are required and the remaining 34 are advisory. All rules apply to the source code and not to the object code generated by the compiler. MISRA C 2004121 RULES REQUIRED20 RULES ADVISORY21 CategoriesMISRA C 2004 CategoriesIn the group ‘Conversions’, the use of implicit type conversions as well as redundant explicit casts are prohibited.In the group ‘Expressions’, a rule describes floating-point variables are not to be tested for exact equality or inequality.In the group ‘Control Flow’, the use of goto, break and continue is prohibited. Also a number of constraints on the use of the if, else, switch, and case constructs is defined.The group ‘Pointers and Arrays’ prohibits the use of non-constant pointers to functions and discourages the use of pointer arithmetic at all.The group ‘Structures and…

Simulation of D Flip Flop and J-K Flip Flop

Requirements:WARP Active HDL Cool Runner and Fitter CPLD Kit D Flip FlopProgram for D Flip flop
Library ieee;
Use ieee.std_logic_1164.all;
entity dff is
port (
clk: in BIT;
data: in BIT;
q: out BIT;
qbar: out BIT
);
end dff;
architecture dff of dff is
begin
process(clk,data)
begin
if(clk='1') then
q <= data;
qbar <= not data;
end if;
end process;
end dff;Waveform (D Flip Flop)JK Flip FlopProgram for J-K flip flop
library IEEE;
use IEEE.std_logic_1164.all;
entity jkff is
port (
clk: in STD_LOGIC;
j: in STD_LOGIC;
k: in STD_LOGIC;
q: inout STD_LOGIC;
qbar: inout STD_LOGIC
);
end jkff;
architecture jkff of jkff is
begin
process(clk)
begin
if(clk'event and clk='1') then
if(j = not k) then
q <= j;
qbar <= k;
elsif(j = '1'…