VHDL–3 to 8 Decoder

Decoder is a combinational logic circuit which has ‘n’ inputs and one output out of 2n outputs. for example if there are 3 inputs the decoder asserts one of the 8 inputs to the output. the following diagram shows the 3 to 8 decoder.

image

here is the truth table

A B C Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0   1 0 0 0 0 0 0 0
0 0 1   0 1 0 0 0 0 0 0
0 1 0   0 0 1 0 0 0 0 0
0 1 1   0 0 0 1 0 0 0 0
1 0 0   0 0 0 0 1 0 0 0
1 0 1   0 0 0 0 0 1 0 0
1 1 0   0 0 0 0 0 0 1 0
1 1 1   0 0 0 0 0 0 0 1

Whenever the inputs are 000 then the Q0 will be ON and so on.

VHDL Code for 3 to 8 decoder

Tool used: Active HDL Student Edition 7.2

library ieee;
use ieee.std_logic_1164.all;
 
entity dec3to8 is
  port (sel: in std_logic_vector (2 downto 0);
        res: out std_logic_vector (7 downto 0));
end dec3to8;
architecture archi of dec3to8 is
  begin
    res <=  "00000001" when sel = "000" else
            "00000010" when sel = "001" else
            "00000100" when sel = "010" else
            "00001000" when sel = "011" else
            "00010000" when sel = "100" else
            "00100000" when sel = "101" else
            "01000000" when sel = "110" else
            "10000000";
end archi;

Here is the waveform

decoder

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